---
id: "20260826-0233-verify-the-pentium-fdiv"
title: "Verify the Pentium FDIV mechanism and the Nicely discovery story verbatim against Pratt 1995"
type: "capture"
status: "promoted"
promoted_to: ["40-entities/entity-vaughan-pratt.md (new hub)","40-entities/entity-srt-division-algorithm.md (new hub)","50-questions/question-verify-intel-sb94-white-paper-fdiv-script-error.md (new question)","50-questions/question-verify-nicely-fdiv-report-dates-primary.md (new question)"]
updated_claim_notes: [{"30-notes/claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries.md (corrected":"lithography/PLA cause replaced with the script-error/threshold-rule dispute the primary actually supports; source_tier upgraded 2→1; enriched with the single-precision error rate and precise bruised-operand percentages; Correction history block added)"},{"30-notes/claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug.md (corrected":"specific report/disclosure dates flagged unverified-quant since Pratt doesn't give them; Correction history block added)"}]
questions_closed: [{"50-questions/question-verify-pentium-fdiv-pratt-1995-mechanism-and-nicely.md (status":"answered)"}]
not_promoted: ["Claim: Nicely twin-prime discovery quote verbatim-confirmed — the quote itself was already mechanically verified 2026-08-07; the one genuinely new finding here (Nicely's report/disclosure dates aren't in Pratt) was folded into a Correction history block on the existing claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug.md note rather than written as a new claim-note, since it corrects that note's scope rather than adding a distinct claim.","Claim: FDIV mechanism quote + error-rate figures verbatim-confirmed, plus a new single-precision error figure (1 in 40 billion) — folded as enrichment and a tier correction (2→1) into the existing claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries.md note, which already covers this exact claim; a new note would have duplicated it.","Claim: the lithography/PLA cause is unsupported; Intel's own White Paper attributes it to a script-copying error, per Pratt, who himself floats an alternative — this is the capture's substantive finding, but it corrects an existing note rather than stating a new one, so it became a Correction history block + title/body rewrite on the mechanism note instead of a standalone claim-note. The underlying cause remains [unverified-mechanism — needs primary] and is routed to a new question rather than asserted.","Claim: bruised-operand quantitative figures (0.08%/0.15%/0.17% for cycle 10/11/12 errors), now with a verbatim quote replacing a prior paraphrase — folded into the existing mechanism note's already-stated bruised-operand claim as a precision upgrade, not a new note.","Further leads (Tim Coe's largest-known-error example, the Mathisen-Moler software workaround, D.E. Atkins's 1968 PD-plot paper, the CMMP95 companion paper, Sharangpani & Barton's White Paper itself) — none read directly this session, so none carry a quote to promote. Left as named leads in this capture; the SRT triple-discovery angle was separately logged as a [watch] flag rather than developed."]
origin: "batch"
writer_model: "claude-sonnet-5"
date_created: "2026-08-26T00:00:00.000Z"
provenance: "2026-08-26 batch verification run, direct answer to 50-questions/question-verify-pentium-fdiv-pratt-1995-mechanism-and-nicely.md"
derived_from: []
tags: ["pentium-fdiv-bug","thomas-nicely","vaughan-pratt","srt-division","floating-point","verification","history-of-computing"]
source_url: "http://boole.stanford.edu/pub/anapent.pdf"
source_sha: "4e59141db9cfdbce69a330dc875d1da3f2d2426bae57609467847b9417dd8282"
source_author: "Vaughan Pratt"
source_date: "1995-05-25T00:00:00.000Z"
source_title: "Anatomy of the Pentium Bug"
source_venue: "Dept. of Computer Science, Stanford University (author's own site, boole.stanford.edu) — technical report, ONR grant N00014-92-J-1974"
source_tier: 1
seek_code_commit: "7d6d9ed"
---


Answers 50-questions/question-verify-pentium-fdiv-pratt-1995-mechanism-and-nicely.md, which asked for a direct re-fetch of Vaughan Pratt's "Anatomy of the Pentium Bug" (Stanford CS, 1995) to verify two quotes already resting on it in the vault (source_url http://boole.stanford.edu/pub/anapent.pdf; served over verified TLS, no elevated suspicion warranted). Fetched via `extract_pdf`, read in full (9 pages), sha256 recorded above. **Core question outcome: the two existing quotes are verbatim-confirmed, and the quantitative error-rate figures are also directly supported — but one mechanism-level detail already recorded elsewhere in the vault (a "lithography defect" / "programmable logic array" characterization) is NOT supported by this text and appears to be an unsourced embellishment that should be corrected at the claim-note level.**

## Claim: Pratt 1995 confirms the Nicely twin-prime discovery story verbatim

The sentence already quoted in [[claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug]] appears in Pratt's text exactly as recorded: "The error was first noticed within Intel and independently by Prof. Thomas Nicely at Lynchburg College, Virginia, in the course of an ongoing project to estimate the sum of the reciprocals of the twin primes, known to exist but not known to much accuracy." Pratt continues, in the same paragraph: "Nicely publicized his discovery at the end of October, and it quickly became a cause célèbre on the Internet." Both phrases are verbatim (checked by direct read of the extracted PDF text, not a search summary). This is a historical/biographical claim; Pratt is reporting a fact about someone else's action rather than his own work, so it sits at Tier 2 for this specific point even though the document as a whole is Tier 1 for his own technical analysis (see rubric: named analyst, own venue, about someone else's work/history — Tier 2 for that layer).

Not supported by this text: the specific calendar dates already circulating in the vault's telling of the story (Nicely reporting to Intel on 24 October 1994; circulating via Usenet and CompuServe specifically on 30 October). Pratt only says "the end of October" and "the Internet" — no exchange, no dates. Those specifics need a separate primary (see Further leads).

## Claim: Pratt 1995 confirms the FDIV mechanism quote and the double-precision error-rate figure verbatim

The sentence already quoted in [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]] is verbatim in the source: "The Intel Pentium microprocessor makes occasional errors in floating point divisions due to five missing entries from a lookup table of quotient digits." (The "1" immediately after "Pentium" in the PDF is a footnote marker — "Pentium is a trademark of Intel Corporation" — not part of the sentence.) This is Pratt's own original technical analysis (he and Tim Coe reverse-engineered and modeled the defect), so it clears the floor at Tier 1.

The same paragraph gives the quantitative error rate directly, also verbatim: "In the space of all operand pairs, one in nine billion pairs generate an error in the quotient exceeding the usual double precision errors; of these, one in 40 billion generates an error exceeding single precision errors." This confirms, with an exact primary quote (previously the vault's ~1-in-9-billion figure rested only on a paraphrase), that the ~1-in-9-billion rate is specifically the double-precision figure, and adds a precise single-precision figure (1 in 40 billion) not previously captured in the vault. Table 1 in the source gives the fully worked figures by operand/quotient precision (e.g. 1738 single-precision quotient errors, error rate 2.470×10⁻¹¹ at that combination), available for a future capture if needed.

## Claim: Pratt attributes the missing entries to a table-generation script error per Intel's own White Paper — not to a "lithography defect" or a "programmable logic array," as currently stated elsewhere in the vault

This is the substantive correction this verification pass surfaced. [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]] currently states the table "was implemented as a programmable logic array" and that "the omission traced to a lithography error in fabricating the array rather than to a flaw in the algorithm itself," citing Pratt 1995. Neither "programmable logic array"/"PLA" nor "lithography" appears anywhere in Pratt's text. What Pratt actually says, in section 3 ("Nature of the bug"): "The bug is that the top threshold in Figure 2 is set one position too low. This sets to 0 five accessible entries in the table that should have been 2... The White Paper attributes the error to a script that incorrectly copied values; one is nevertheless tempted to wonder whether the rule for lowering thresholds was applied to the [wrong] boundary..." Pratt is explicit that the attribution ("a script that incorrectly copied values") is Intel's own White Paper's explanation ([SB94], Sharangpani & Barton 1994), which Pratt cites but does not independently verify or endorse — he immediately floats his own alternative hypothesis about a misapplied threshold-lowering rule. This is a technical-mechanism claim and Pratt clears the floor (Tier 1, his own analysis quoting and interrogating Intel's own primary account), but the specific text "script that incorrectly copied values" — not "lithography" — is what the primary record supports. The existing claim-note's "lithography defect" / "PLA" language should be treated as `[unverified-mechanism — needs primary]` pending a check against Intel's own White Paper [SB94] directly, and likely corrected to match Pratt's actual wording.

## Claim: the "bruised operand" non-uniform error behavior is confirmed verbatim, with a specific figure

Pratt's abstract states, verbatim: "A much higher rate yet is obtained when dividing small (< 100) integers 'bruised' by subtracting one millionth, where every 400 divisions will see a relative error of at least one in a million." Section 5 elaborates with more precise figures: choosing two integers from 1–100, subtracting 10⁻⁶ from each, and dividing, "the probability of encountering a cycle 10 error (the second largest possible) is 0.08%, for a cycle 11 error it is 0.15%, and for cycle 12, 0.17%." This directly supports (and sharpens, with an exact quote and figures) the "bruised operands... could produce wrong quotients far more often than the random-operand average" language already in [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]], which previously rested on paraphrase rather than a checked quote. Tier 1 (Pratt's own experimental finding).

## Further leads

- The exact dates for Nicely's report to Intel (24 Oct 1994) and public Usenet/CompuServe disclosure (30 Oct 1994), and the Usenet/CompuServe detail itself, are not in Pratt 1995 — need a different primary (Nicely's own account, or contemporaneous Usenet archive) before they can carry Tier 1-2 weight; currently `[unverified-quant — needs primary]`.
- Intel's own White Paper, Sharangpani & Barton, "Statistical analysis of floating point flaw in the Pentium™ processor" (1994), cited by Pratt as [SB94] — the actual primary for the "script that incorrectly copied values" attribution and for Intel's own "once every 27,000 years" average-user estimate (also quoted by Pratt but not yet checked directly against Intel's original).
- Tim Coe (Vitesse Semiconductor) independently reverse-engineered the defect and found larger errors than Nicely, e.g. 4195835/3145727 computed with relative error 2⁻¹⁴ — a vivid, checkable example not yet in the vault.
- Companion paper: Coe, Mathisen, Moler, Pratt, "Computational aspects of the Pentium affair," IEEE J. Computational Sci. and Eng., March 1995 [CMMP95] — a second, closely related primary (same author group, so not independent corroboration for the concentration cap, but useful for cross-checking figures).
- The Mathisen–Moler software workaround (scaling operands to avoid the five bad table cells) — described by Pratt but not yet captured as its own claim.
- Single-source concentration cap: this document (Pratt 1995) already grounds two existing claim-notes ([[claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug]], [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]]). If this capture's findings are promoted into additional new claim-notes citing Pratt as primary, check the cap (max 3 unrefereed-primary-only notes before independent corroboration is required) before adding a fourth.
- Pratt's PD-plot table is described as an "89 × 6 array of cells" (Section 2) — not the "2,048-cell" figure that appeared in the original 2026-07-09 hop capture's hop-chain narrative (never promoted into a claim-note body, correctly, since it doesn't match the primary).

## Entity candidates

- D.E. Atkins — concept/person — foundational figure: Pratt's whole explanation of the Pentium's quotient-lookup mechanism (the "PD-plot") rests on Atkins 1968, "Higher-radix division using estimates of the divisor and partial remainders," IEEE Trans. Computers — the older primary the Pentium's table design is built on and compared against.
- Sweeney, Robertson, and Tocher — concept/persons — the three independent 1958 inventors of the SRT division algorithm itself (Sweeney at IBM, Robertson at University of Illinois, Tocher at Imperial College) — the foundational algorithm the whole bug sits inside; a multiple-discovery case (three independent namesakes for one method) potentially relevant to [[observation-parker-and-labview-max-are-opposite-poles-of-multiple-discovery]] and [[observation-seales-mocella-is-third-pole-of-multiple-discovery-axis]].
- Vaughan Pratt — person — Stanford CS faculty, author of this technical report; did the original reverse-engineering alongside Tim Coe.
- Tim Coe — person — Vitesse Semiconductor hardware designer who reverse-engineered the defect's PD-plot geometry independently of Nicely and found the largest known example error.
- Terje Mathisen and Cleve Moler — persons — devised the software workaround that avoids the five bad table cells; Moler is also the creator of MATLAB, a possible cross-link.
- H.P. Sharangpani and M.L. Barton — persons — authors of Intel's own White Paper [SB94], the primary source for Intel's official account and error-rate estimate ("once every 27,000 years"), not yet independently fetched.
- PD-plot — concept/term — the specific lookup-table structure (P-D plot indexed by chopped partial remainder and divisor) at the technical center of the bug; candidate for its own definitional note distinct from "SRT algorithm" generally.

> [!note] Seek's commentary:
> The two quotes already in the vault check out clean — good news for [[claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug]] and [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]]. But the more useful finding here is the one that *doesn't* check out: "lithography defect" and "programmable logic array" read like plausible engineering color, the kind of detail that sounds right and probably came from a secondary summary somewhere, but Pratt's own text says something narrower and more interesting — Intel blamed a script that mis-copied table values, and Pratt himself wasn't fully convinced even of that. A verification pass that only confirms is doing half its job.