---
title: "A 2021 ISSCC paper from Naveen Verma's lab is peer-reviewed primary evidence for EnCharge's switched-capacitor mechanism, but not for the EN100 product's efficiency figures"
type: "claim"
status: "seedling"
writer_model: "claude-sonnet-5"
source_url: "https://www.princeton.edu/~nverma/VermaLabSite/Publications/2021/JiaOzatayTangValaviPathakLeeVerma_ISSCC2021Proof.pdf"
source_sha: "b35925b19bf59a796894eebc3a5a58ede470455c7d86408a3d7851ab5e22e69c"
source_title: "A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing"
source_author: "Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma"
source_date: "2021-02-17T00:00:00.000Z"
source_venue: "2021 IEEE International Solid-State Circuits Conference (ISSCC), Session 15.1"
source_tier: 1
source_quote: "achieving peak efficiency and throughput exceeding previously-reported accelerators"
provenance: "Promotion from 10-inbox/raw/2026-07-31-do-encharge-en100s-200-tops-825-w-and.md, 2026-07-31"
origin: "batch"
derived_from: ["10-inbox/raw/2026-07-31-do-encharge-en100s-200-tops-825-w-and.md"]
date_created: "2026-07-31T00:00:00.000Z"
tags: ["analog-computing","ai-hardware","in-memory-compute","encharge","isscc","benchmark","verma"]
related_notes: ["claim-encharge-en100-switched-capacitor-in-memory-compute","claim-no-independent-benchmark-of-encharge-en100-efficiency-figures","claim-tpu-matrix-unit-called-heart-of-the-tpu"]
---


EnCharge's switched-capacitor architecture descends from [[claim-encharge-en100-switched-capacitor-in-memory-compute|Naveen Verma's Princeton lab]]. The clearest Tier-1 primary artifact behind it is Jia, Ozatay, Tang, Valavi, Pathak, Lee & Verma, "A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing," presented at ISSCC 2021 (Session 15.1, Feb 17 2021): a 16 nm, 25 mm² prototype using the same metal-fringing-capacitor, charge-domain multiply mechanism later commercialized as the EN100. The paper compares its own chip against seven named prior accelerators from ISSCC/VLSI/JSSC 2016–2020, stating it as "the only IMC demonstration for scalable NN execution, while achieving peak efficiency and throughput exceeding previously-reported accelerators."

This is real, peer-reviewed, independently-refereed evidence that the underlying **mechanism** — switched-capacitor charge-domain in-memory compute — has a documented efficiency record. It is *not* evidence for the EN100 product's specific 200 TOPS/8.25 W or "20x" figures ([[claim-no-independent-benchmark-of-encharge-en100-efficiency-figures]]): the 2021 chip is a different silicon generation and die size, uses a different precision regime (4-bit weights/activations for its measurements vs. the EN100's INT8 product spec), predates the 2025 commercial part by four years, and its own comparison set is other academic prototypes — not the "competing solutions" EnCharge's marketing multiplier is measured against ([[claim-encharge-en100-20x-per-watt-claim-has-no-stated-baseline]]). The paper's comparison table contains numeric TOPS/W figures per competitor, but extracted-PDF text rendered the table's alignment ambiguously (footnote markers fused to digits); only the paper's unambiguous prose claim is recorded here to avoid misquoting a garbled table.

> [!note] Seek's commentary:
> This is the useful distinction the capture earns: there genuinely is a Tier-1 paper trail behind EnCharge's story, it just underwrites the *idea* (capacitors beat memristors on precision) rather than the *product* (this specific chip hits these specific watts). Conflating the two is the easy mistake — five years and one commercialization step separate a refereed academic claim from a marketing number, and only one of them has been checked by anyone outside the company.
> — Seek