---
title: "EnCharge AI's EN100 does in-memory matrix multiplication with lithography-defined switched capacitors rather than memristors, deriving precision from wire geometry instead of device conductance"
type: "claim"
status: "seedling"
audit_status: "capture-verified | 2026-07-12 cross-model audit (claude-fable-5): IEEE Spectrum article re-fetched — both mechanism quotes (geometry/space-between-wires; same-voltage-different-conductance) verbatim-confirmed, switched-capacitor-not-RRAM mechanism and Verma/Princeton origin confirmed, 200 TOPS @ 8.25 W and up-to-20x/W confirmed as company claims carried by the article. CORRECTED: body said the EN100 'shipped' in 2025; the article (June 2025) says it was with early-access developers — softened to match. [unverified-quant] flag stands"
writer_model: "claude-opus-4-8"
flags: ["[unverified-quant] The 200 TOPS at 8.25 W and 'up to 20x performance per watt' figures are company-sourced, reported through a Tier-2 journalism piece with no independent benchmark. Kept seedling; verification routed to [[question-verify-encharge-en100-efficiency-primary]]."]
source_url: "https://spectrum.ieee.org/analog-ai-chip-architecture"
source_title: "EnCharge's Analog AI Chip Promises Low-Power and Precision"
source_author: "IEEE Spectrum (reporting; quoting Naveen Verma, EnCharge AI / Princeton)"
source_date: 2025
source_quote: "the only thing they depend on is geometry, basically the space between wires... the one thing you can control very, very well in CMOS"
source_tier: 2
provenance: "Promotion from 10-inbox/raw/2026-07-11-hop-analog-nn-inference-silicon.md, 2026-07-11"
origin: "hop-batch"
derived_from: ["10-inbox/raw/2026-07-11-hop-analog-nn-inference-silicon.md"]
date_created: "2026-07-11T00:00:00.000Z"
tags: ["analog-computing","ai-hardware","in-memory-compute","inference","switched-capacitor","memristor","cmos","hardware-history"]
related_notes: ["claim-reconfigurable-analog-computers-target-differential-equations-not-neural-networks","claim-processing-in-memory-beats-memory-wall-dna-alignment","claim-memory-wall-named-1994-wulf-mckee","claim-inference-dominant-ai-compute-2026"]
---


**EnCharge AI** — spun out of Naveen Verma's Princeton lab — brought an analog **in-memory compute** inference chip, the **EN100**, to early-access developers in 2025, aimed at laptop and edge use. It performs matrix–vector multiplication where the data lives, but its mechanism inverts the canonical analog-AI story. The dominant analog-AI approach uses **resistive memory** (RRAM/memristors), encoding weights as programmable device conductances. EnCharge instead uses metal-wire **switched capacitors**, doing the multiply through physical charge-sharing.

The rationale is precision. Resistive-memory conductances drift and vary: "you could set the exact same voltage on two cells... and those two cells would wind up with slightly different conductance values." Capacitors escape this because "the only thing they depend on is geometry, basically the space between wires... the one thing you can control very, very well in CMOS." Precision is therefore defined by **lithographic geometry** — the digital fab's home turf — rather than by the material state of a memory device.

The reported performance is 200 TOPS at 8.25 W and "performance per watt up to 20 times better than competing chips." These figures are company-sourced and reach the vault only through Tier-2 journalism, so they are held as `[unverified-quant]` pending an independent or primary benchmark (see [[question-verify-encharge-en100-efficiency-primary]]).

Placing the multiply inside the memory is one architectural response to the [[claim-memory-wall-named-1994-wulf-mckee|memory wall]] — the same family of idea as [[claim-processing-in-memory-beats-memory-wall-dna-alignment|processing-in-memory hardware]], and aimed at the workload the vault tracks as [[claim-inference-dominant-ai-compute-2026|the now-dominant AI compute cost]]. It belongs to a lineage **distinct** from the differential-equation analog computers of [[claim-reconfigurable-analog-computers-target-differential-equations-not-neural-networks]].

> [!note] Seek's commentary:
> The tell is that EnCharge's pitch is anti-analog in spirit: it retreats from the noisy, physics-native part of analog (device state) to the part CMOS already nails (geometry). "Analog computing" here means *where* the multiply happens — in memory, in physical charge-sharing — not a return to imprecise continuous state. The mechanism claim is Tier-2 but coherent and quotable; it is the numbers, not the story, that I refuse to bless without a primary.
> — Seek