---
title: "Google's TPU paper calls its 65,536-MAC systolic matrix-multiply unit 'the heart of the TPU,' using systolic execution to cut Unified Buffer reads/writes"
type: "claim"
status: "seedling"
writer_model: "claude-sonnet-5"
audit_status: "capture-verified"
source_url: "https://arxiv.org/pdf/1704.04760"
source_title: "In-Datacenter Performance Analysis of a Tensor Processing Unit"
source_author: "Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, et al. (Google)"
source_date: "2017-06-26"
source_quote: "The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS)... the matrix unit uses systolic execution to save energy by reducing reads and writes of the Unified Buffer [Kun80]."
source_tier: 1
provenance: "Promotion from 10-inbox/raw/2026-07-11-hop-systolic-array-heart.md, 2026-07-12"
origin: "batch"
derived_from: ["10-inbox/raw/2026-07-11-hop-systolic-array-heart.md"]
date_created: "2026-07-12T00:00:00.000Z"
tags: ["TPU","systolic-array","hardware","matrix-multiply","google","cardiac-metaphor","AI-inference"]
related_notes: ["claim-systolic-array-named-after-cardiac-systole","claim-tpu-most-nn-workloads-memory-bandwidth-bound","claim-roofline-model-compute-bound-vs-memory-bound","claim-inference-dominant-ai-compute-2026"]
drafted_in: ["2026-07-13-the-heart-was-always-a-pump","the-heart-was-always-a-pump"]
---


Google's 2017 TPU paper, "In-Datacenter Performance Analysis of a Tensor Processing Unit" (Jouppi, Patterson, et al.), describes the chip's central compute block in explicitly cardiac language: "The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS)." The unit is a **systolic array** in the Kung & Leiserson (1978) sense — the paper cites Kung's foundational work directly ("[Kun80]") — and the authors state the mechanism explicitly: "the matrix unit uses systolic execution to save energy by reducing reads and writes of the Unified Buffer."

The energy-saving mechanism is structural: because each processing element in the array passes partial results directly to its neighbor on a fixed rhythm, intermediate values do not need to be written back to and re-read from a shared on-chip memory (the Unified Buffer) at every step, the way a conventional load/store architecture would require. Fewer memory accesses for the same computation is the systolic design's core efficiency argument, independent of any particular application.

This is a case of a decades-old cardiac metaphor closing its own loop: H.T. Kung named the architecture after the heart in 1978–1982 ([[claim-systolic-array-named-after-cardiac-systole]]), and Google's engineers, almost certainly without invoking that etymology deliberately, called the resulting AI-accelerator component "the heart of the TPU" in 2017.

> [!note] Seek's commentary:
> Worth separating cleanly from the naming claim: this note only asserts what the TPU paper itself says about its own hardware (a Tier-1, directly-verified quantitative and mechanism claim), not the etymological backstory. The two notes reinforce each other but rest on independent, differently-tiered evidence.
> — Seek