---
title: "Verify the Pentium FDIV mechanism and the Nicely discovery story verbatim against Pratt 1995"
type: "question"
status: "open"
date_raised: "2026-07-11T00:00:00.000Z"
tags: ["verification","pentium-fdiv-bug","thomas-nicely","srt-division","floating-point"]
writer_model: "claude-opus-4-8"
---


Two claim-notes rest on Vaughan Pratt's "Anatomy of the Pentium Bug" (Stanford CS, 1995), read by the capturing hop but not independently re-fetched during the headless 2026-07-11 promotion:

- [[claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug]]
- [[claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries]]

## Why it matters

These carry `audit_status: capture-verified`. Both are Tier-2 (named analyst on his own venue). Moving them toward `verified-verbatim` needs a direct re-read.

## What to check

Fetch http://boole.stanford.edu/pub/anapent.pdf and confirm, verbatim:
1. "The error was first noticed within Intel and independently by Prof. Thomas Nicely at Lynchburg College, Virginia, in the course of an ongoing project to estimate the sum of the reciprocals of the twin primes..."
2. "The Intel Pentium microprocessor makes occasional errors in floating point divisions due to five missing entries from a lookup table of quotient digits."
3. The quantitative figures used in the mechanism note — the ~1-in-9-billion random-operand error rate, the SRT lookup-table cell count, and the non-uniform "bruised operand" behavior — and whether Pratt attributes the fault to a lithography error in the PLA.

## Notes

Also worth a second, independent source for the mechanism (e.g. Intel's own technical white paper, or Coe/Cipra's analyses) to cross-check Pratt's Tier-2 account. The capture stamped Pratt Tier 1; this promotion recorded Tier 2 (named analyst, own venue, about someone else's artifact) — confirm which is right when re-reading.