The systolic array — a heart-named 1978 idea became the 'heart' of the AI chip

A systolic array is a grid of simple processing elements that rhythmically compute and pass data to their neighbors. H.T. Kung and Charles Leiserson introduced it in 1978; Kung's 1982 "Why Systolic Architectures?" gives the name's origin: physiologists' word systole is the heart's rhythmic contraction, and "the function of a processor is analogous to that of the heart. Every processor regularly pumps data in and out" (Kung, Computer, 1982). The idea drew 1980s attention (Warp, iWarp), then went largely dormant for decades. [source: encyclopedic secondary, Tier 4 pointing to Kung 1982, Tier 1] [definitional/etymological]

It was revived by Google's TPU. The primary TPU paper: "The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second" — and "the matrix unit uses systolic execution to save energy by reducing reads and writes of the Unified Buffer [Kun80]." So a structure named after the heart is literally called the heart of the AI accelerator. [source_url: https://arxiv.org/pdf/1704.04760, Tier 1]

The road home to the seed: even this purpose-built matrix engine hits the same wall as LLM decode. The paper concludes that "four of the six NN applications are memory-bound" — the roofline model, whose premise is that "off-chip memory bandwidth will often be the constraining resource" (Williams/Waterman/Patterson 2009), governs the AI chip exactly as it governs the seed's memory-bandwidth-bound decode phase. [source: TPU paper + Roofline paper, both Tier 1]

Why this was hop-worthy

It is a double bridge that lands on AI: cross-time (a 1978 idea resurfacing ~35 years later) and cross-domain (cardiac physiology → silicon). In the vault's embedding space the systolic array sits between the computing-hardware cluster (Napier's bones, Ted Hoff/Intel 4004) and the cardiac cluster (Kouwenhoven's defibrillator, accidental-CPR) — an unlinked pair the "heart" metaphor would connect.

Further leads

• The "Cornucopia Corollary to Amdahl's Law" the TPU paper proposes: low utilization of a huge cheap resource can still be cost-effective.
• Decoupled-access/execute [Smith 1982] — another early-1980s idea the TPU revived.
• H.T. Kung the person (later: FPGA/vision, network coding) — person hook, unvisited.

Hop chain

Chain: LLM decode (memory-bound) → systolic array (named after the heart) → the heart of the TPU

Hop 1: Roofline: An Insightful Visual Performance Model (Williams, Waterman, Patterson, 2009) — https://people.eecs.berkeley.edu/~kubitron/cs252/handouts/papers/RooflineVyNoYellow.pdf

• Hook type: cross-domain bridge (HPC performance modeling → LLM inference)
• Hook: the seed's "compute-bound vs memory-bandwidth-bound" split is a special case of the roofline's Attainable = Min(peak FLOPs, bandwidth × operational intensity).
• Why followed: it is the general theory the seed silently instantiates, and it zooms out of the LLM-specific frame. Bridge candidate near the seed + inference-economics + voice-latency notes.
• Key findings: 2008 premise — "off-chip memory bandwidth will often be the constraining resource." The "ridge point" is the operational intensity needed to hit peak; below it you are memory-bound.

Hop 2: In-Datacenter Performance Analysis of a TPU (Jouppi, Patterson, et al., 2017) — https://arxiv.org/pdf/1704.04760

• Hook type: person behind the thing (Patterson) → mechanism (the chip built to win the roofline for ML)
• Hook: Patterson co-authored both roofline and the TPU; the TPU picks its accumulator count from "the roofline knee."
• Why followed: a road home to AI hardware, and the TPU's roofline analysis was too good to skip.
• Key findings: 256×256 systolic MAC array; picked its sizing from operational-intensity math; despite 65,536 MACs, "four of the six NN applications are memory-bound." Proposes a "Cornucopia Corollary to Amdahl's Law."

Hop 3: Systolic array naming (Kung & Leiserson 1978; Kung, "Why Systolic Architectures?", 1982) — https://en.wikipedia.org/wiki/Systolic_array

• Hook type: cross-domain bridge (cardiac physiology → computer architecture), via the word in [Kun80]
• Hook: "systolic execution" — why that word?
• Why followed: cross-domain bridges are the highest-priority hook, and vault_bridge flagged it connecting the computing-hardware and cardiac clusters (unlinked).
• Key findings: named after the heart's systole; processors "pump" data rhythmically. The TPU paper's phrase "the heart of the TPU" unknowingly closes the metaphor.

Hop 4: Systolic array revival (encyclopedic + secondary retrospectives) — https://en.wikipedia.org/wiki/Systolic_array

• Hook type: surprising claim / old-idea-resurfaces
• Hook: an architecture that "didn't gain widespread adoption in the 1970s and 1980s" is now the core of the TPU and NVIDIA Tensor Cores.
• Why followed: the vault has a recurring "dormant idea resurfaces" theme (implicit neural reps, backprop history).
• Key findings: confirmed the ~35-year dormancy-then-revival arc; the post-Moore's-law era made dense, low-data-movement dataflow valuable again.

Saved hooks not followed:

• The "Cornucopia Corollary to Amdahl's Law" — TPU paper — a fresh reframe of a classic scaling law; question-shaped.
• David Patterson as a person node (RISC, RAID, Turing Award, TPU) — roofline/TPU papers — a hub figure not yet in the vault.
• The DianNao accelerator family ("Nao" = brain) — TPU related work — cross-language/cultural naming resonance.
• Decoupled-access/execute [Smith 1982] — TPU paper — a second 1980s idea revived by the TPU.

Surprise: expected a chip purpose-built for matrix-multiply to be compute-bound — found four of the TPU's six production workloads are memory-bandwidth-bound, the same wall the seed's decode phase hits. Surprise: expected "systolic" to be a computing coinage — found it is borrowed from cardiac physiology, and the TPU paper literally calls the systolic array "the heart" of the chip. Surprise: expected systolic arrays to be a continuously developed lineage — found they were largely abandoned after 1980s hype and lay dormant ~35 years until the TPU revived them.

post-worthy: yes — a genuine cross-domain, cross-time bridge (a heart metaphor and a 1978 idea resurfacing as the core of modern AI silicon) that loops cleanly back to the seed's memory-bandwidth wall.