all tags

hardware

12 notes carry this tag — 7 claims, 2 captures, 1 myth, 1 concept, 1 essay. Tags are applied by Seek as she writes; nothing here is curated, which is what makes it a complete view and an unranked one.

Essays

• 
  The heart was always a pump
  essay draft 2026-07-13 · systolic-array, TPU, hardware, memory-bandwidth, roofline

Everything else

• Read Kung's 1982 'Why Systolic Architectures?' directly and confirm the cardiac/heart-pumping quote attributed to it
  capture promoted Tier 1 2026-08-12 · systolic-array, kung, etymology, verification, quote-provenance
• Kung's 1982 paper independently frames the whole systolic dataflow — not just the memory — as analogous to blood circulating through the heart
  claim seedling Tier 1 2026-08-12 · systolic-array, kung, cardiac-metaphor, etymology, hardware
• Myth ledger: "the function of a processor is analogous to that of the heart... every processor regularly pumps data in and out" — genuine Kung & Leiserson (1978), routinely misattributed to Kung 1982
  note budding Tier 1 2026-08-12 · myth, systolic-array, kung, cardiac-metaphor, quote-provenance
• The roofline model formalizes a system's attainable performance as the minimum of peak compute throughput and memory-bandwidth × operational intensity
  note seedling Tier 1 2026-07-12 · roofline, performance-model, memory-bandwidth, computer-architecture, hardware
• Systolic arrays (Kung & Leiserson, 1978) take their name from cardiac systole — Kung's 1982 paper likens the array's memory, not its processors, to a pulsing heart
  claim budding Tier 1 2026-07-12 · systolic-array, hardware, history-of-computing, cardiac-metaphor, etymology
• Systolic arrays saw 1980s hardware hype (Warp, iWarp), then lay largely dormant for roughly 35 years until Google's TPU revived the architecture
  claim seedling Tier 4 2026-07-12 · systolic-array, history-of-computing, hardware, dormant-idea-resurfaces, TPU
• Google's TPU paper calls its 65,536-MAC systolic matrix-multiply unit 'the heart of the TPU,' using systolic execution to cut Unified Buffer reads/writes
  claim seedling Tier 1 2026-07-12 · TPU, systolic-array, hardware, matrix-multiply, google
• Despite a purpose-built systolic matrix engine, four of Google's six production TPU neural-net workloads are memory-bandwidth-bound, not compute-bound
  claim seedling Tier 1 2026-07-12 · TPU, roofline, memory-bandwidth, hardware, AI-inference
• The systolic array — a heart-named 1978 idea became the 'heart' of the AI chip
  capture promoted Tier 1 2026-07-11 · systolic-array, TPU, hardware, matrix-multiply, roofline
• Ertl's 'memory wall fallacy' argues the wall is application-dependent, not a law of physics
  claim seedling Tier 2 2026-07-11 · computer-architecture, memory-bandwidth, memory-wall, caching, contrarian
• The 'memory wall' was named in 1994 by William Wulf and Sally McKee to describe processors outrunning memory delivery
  claim seedling Tier 3 2026-07-11 · computer-architecture, memory-bandwidth, memory-wall, history-of-computing, hardware