Verify Intel's own White Paper (Sharangpani & Barton 1994) directly for the FDIV table-generation script-error attribution

pentium-fdiv-bugsb94srt-divisionfloating-pointintelverificationhistory-of-computingscript-error

Answers question-verify-intel-sb94-white-paper-fdiv-script-error (via 50-questions/question-verify-intel-sb94-white-paper-fdiv-script-error.md), which asked for a direct read of H.P. Sharangpani and M.L. Barton's Intel White Paper — cited by Vaughan Pratt as [SB94] — since the vault's existing mechanism note (claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries) carried the script-error cause only on Pratt's Tier-2-for-that-layer report of Intel's document, not on the document itself.

Sourcing note on venue. Intel's original hosting location (intel.com/procs/support/pentium/fdiv/white11.ps) is dead. A Wayback Machine index confirms 13 captures of that URL between 21 Dec 1996 and 22 Apr 2024, but the raw .ps content itself timed out on repeated archive_page fetch attempts (both the bare capture URL and the id_-suffixed raw-content variant) — a known-blocked route, not unlike rand.org or ethw.org elsewhere in the vault's sourcing notes. The document was instead read from ardent-tool.com, a vintage-hardware-documentation site hosting a clean 32-page PDF reproduction of the same white paper (verified TLS, tls:"verified" per extract provenance, no elevated suspicion). Page count, title-page wording, author affiliations, and document reference number (941130-1.1) all match the original as described in secondary literature, and the full 32 pages were read directly via extract_pdf (no summarizing layer). This is the best available reading of Intel's original text pending a working route to the Wayback-held original.

Claim: Intel's own White Paper attributes the missing lookup-table entries to a script error in downloading values into a hardware PLA, in its own words

Section 4.2, "The Underlying Cause," states directly: "After the quantized P-D plot (lookup table) was numerically generated as in Figure 4-1, a script was written to download the entries into a hardware PLA (Programmable Lookup Array). An error was made in this script that resulted in a few lookup entries (belonging to the positive plane of the P-D plot) being omitted from the PLA. The 5 critical entries are shown in Figure 4-3 as the shaded regions." This directly confirms, verbatim and from the primary document itself, what claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries had previously carried only on Pratt's secondary report of Intel's account. It is a specific technical-mechanism claim and Intel's own document — the entity that built the part, describing its own defect — clears the Tier 1-2 floor outright (Tier 1: primary, high-method).

One terminology correction falls out of this direct read: Intel's own text spells out "PLA" as "Programmable Lookup Array," not "Programmable Logic Array" as an earlier (now-corrected) version of the vault's mechanism note had stated before that language was removed for lacking a source. The two terms describe genuinely different things (a lookup table download target vs. a logic-synthesis fabric), so this is not a trivial wording fix — the earlier phrasing, even though wrong on its exact words, was closer to Intel's real explanation than the "lithography defect" framing it was replaced with, and Intel's document confirms the flaw is a data-loading/scripting error, not a fabrication-process (lithography) defect.

Claim: Intel's White Paper does not address, or even mention, the alternative "misapplied threshold-lowering rule" hypothesis Pratt raises

Pratt's 1995 paper cites Intel's script-error attribution and then adds, unprompted, his own competing conjecture: "one is nevertheless tempted to wonder whether the rule for lowering thresholds was applied to the [wrong] boundary." A full direct read of all 32 pages of Sharangpani & Barton (sections 1 through 9 plus Appendix A) contains no discussion of a threshold-lowering rule, no hedging on the script-error account, and no mention of any alternative cause. The word "threshold" does not appear anywhere in the document. This confirms that Pratt's alternative hypothesis is his own speculation, entirely absent from Intel's own account — Intel's document is unambiguous and singular in its explanation. This is a claim about the contents (and non-contents) of a specific document, sourced directly by full-text read of the Tier 1 primary rather than a quote of absence.

Claim: Intel's White Paper independently states the ~1-in-9-billion / 1.14×10⁻¹⁰ failure-probability figure that Pratt also quotes

Section 3 states: "Characterization based on two independent methods consistently yields a probability that 1 in 9 billion randomly fed divide or remainder instructions will produce inaccurate results. The fraction of the total input number space that is prone to failure is 1.14 x 10 -10." Section 6.3.1 restates the same figure in a different context: "The probability P1 is known from the studies cited earlier in this report. It works out to 1 in 9 billion or 1.11E-10." (The two decimal renderings, 1.14×10⁻¹⁰ and 1.11E-10, appear in different sections of the same document without reconciliation — both are Intel's own figures, not a vault transcription error.) This is a quantitative claim and clears the floor directly: Intel's own document is the primary source Pratt was citing when he separately reported "one in nine billion pairs" in claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries.

Claim: Intel's White Paper independently confirms the "once every 27,000 years" average-user estimate

Section 6.2.1 states: "an average PC user invoking 1,000 divides per day would see a FIT rate of once in 27,000 years due to this failure mechanism." Table 5-1 and the Conclusions section (item 2) both restate the identical figure: "The average PC user is likely to encounter a failure once in 27,000 years due to this flaw." This is Intel's own headline risk-communication number — the calculation Intel used to argue the flaw was inconsequential for ordinary users — and it is now confirmed directly against the primary rather than resting on a secondary's citation of it.

Further leads

• Original Intel URL (intel.com/procs/support/pentium/fdiv/white11.ps) is dead; its Wayback Machine capture index (13 snapshots, 1996–2024) is reachable but the raw content times out on tooling — worth a manual-consultation retry in a future session.
• Alan Edelman, "The Mathematics of the Pentium Division Bug," SIAM Review (1997), https://math.mit.edu/~edelman/homepage/papers/pentiumbug.pdf — a technically independent author and venue from both Pratt and Intel; a candidate for genuine independent corroboration of the SRT/PD-plot mechanism, not yet read directly.
• Appendix A of Intel's White Paper lists ~30 engineering/scientific constants (Avogadro's number, Planck's constant, speed of light, etc.) tested as literal divisors against the flaw, with two initially flagged as at-risk and then cleared by 100 billion random-dividend trials — a candidate for its own note on how Intel validated the flaw's practical harmlessness.
• Section 6.3.2 gives Intel's own MTBF estimates for financial-engineering use cases (Black-Scholes, Monte Carlo path simulations, e.g. "the upper bound... is about 1 billion divisions per day yielding an MTBF of 9 days") — not yet captured, and a sharper quantitative source than any secondary summary of "Intel worried about financial users."
• Companion paper Coe, Mathisen, Moler, Pratt, "Computational aspects of the Pentium affair," IEEE J. Computational Sci. and Eng. (March 1995) [CMMP95] — still not fetched; shares an author with Pratt 1995, so not independent corroboration, but useful for cross-checking figures.
• Single-source concentration cap: this capture's claims all rest on Sharangpani & Barton 1994, an unrefereed corporate primary (Intel's own internal white paper, not peer-reviewed). If promoted as new claim-notes rather than folded into the existing mechanism note, check the cap (max 3 notes on one unrefereed primary before independent corroboration) — Edelman 1997 above is the strongest candidate for discharging it if read directly in a future session.

Entity candidates

• D. Sweeney (IBM), J.E. Robertson (University of Illinois), and T.D. Tocher (Imperial College London) — persons — Intel's own document credits them by name, in a footnote, as the three independent 1958 co-discoverers of the SRT algorithm the Pentium's divider implements; the foundational method the whole defect sits inside, and the figures the note's subject (Intel's engineering account) is implicitly measured against.
• Daniel E. Atkins — person — author of the 1968 IEEE Transactions on Computing paper ("Higher-Radix Division Using Estimates of the Divisor and Partial Remainders") that Intel cites as reference [2], its own technical source for the SRT/PD-plot method it implemented and later found defective.
• H.P. Sharangpani — person — Numerics Architect and Project Leader, Microcode & Algorithm Development, Pentium Processor Development Team, Intel Corporation; co-author of the White Paper.
• M.L. Barton — person — Staff Computational Scientist, Software Technology Lab, Intel Corporation; co-author of the White Paper.
• Peter Tang (Argonne National Laboratory) — person — credited in Intel's Acknowledgments for "analytically and experimentally characterizing the hardware algorithm and the flaw"; an external numerical-analysis figure brought in to check Intel's own account.
• Programmable Lookup Array (PLA) — concept/term — Intel's own name for the hardware structure the PD-plot lookup table was downloaded into; distinct from the more commonly known "Programmable Logic Array," and worth a definitional note to prevent the terms being conflated again.