The Pentium FDIV bug was five missing entries in the SRT algorithm's quotient-digit lookup table; Intel attributed it to a table-generation script error, not a lithography defect

pentium-fdiv-bugsrt-divisionfloating-pointhardware-defectscript-errornumerical-analysishistory-of-computing

The Pentium performed floating-point division using the SRT algorithm (Sweeney, Robertson, Tocher), which generates several quotient bits per iteration by consulting a lookup table — the "PD-plot," indexed by a chopped partial remainder and divisor — that maps to the next quotient digit. On the affected Pentiums a threshold in that table was set one position too low, zeroing out five entries that should have held a nonzero digit. Per Vaughan Pratt's 1995 analysis, "the Intel Pentium microprocessor makes occasional errors in floating point divisions due to five missing entries from a lookup table of quotient digits" — his own reverse-engineering work with Tim Coe, Tier 1 for this mechanism claim. Intel's own White Paper (Sharangpani & Barton 1994, cited by Pratt as [SB94]) confirms the cause directly, in its own words: "a script was written to download the entries into a hardware PLA (Programmable Lookup Array). An error was made in this script that resulted in a few lookup entries (belonging to the positive plane of the P-D plot) being omitted from the PLA." A full 32-page direct read (2026-08-27) found no hedge on this account and no mention anywhere of Pratt's own alternative hypothesis about a misapplied threshold-lowering rule — see claim-pratts-threshold-lowering-hypothesis-absent-from-intels-fdiv-white-paper — confirming that hypothesis was Pratt freelancing a second guess Intel's own document never raises. Intel's document also independently restates the ~1-in-9-billion failure rate Pratt quotes (as 1.14×10⁻¹⁰ in one section and 1.11×10⁻¹⁰ in another — an internal inconsistency Intel's own text never reconciles) and gives its own average-user risk estimate, treated separately in claim-intel-1994-white-paper-estimated-fdiv-bug-once-per-27000-years.

Because the five bad cells were reached only by particular combinations of operands, the average error rate was extremely low: per Pratt, "one in nine billion pairs generate an error in the quotient exceeding the usual double precision errors; of these, one in 40 billion generates an error exceeding single precision errors" — the ~1-in-9-billion figure is specifically the double-precision rate, and the 1-in-40-billion single-precision figure had not previously been recorded here. The error rate was also highly non-uniform: dividing small (<100) integers "bruised" by subtracting one millionth from each produced, per Pratt's own testing, "a relative error of at least one in a million" every 400 divisions, with a 0.08% probability of a "cycle 10" error, 0.15% for cycle 11, and 0.17% for cycle 12 — orders of magnitude above the random-operand average, which is why a systematic computation like a reciprocal sum surfaced the defect (see claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug) while ordinary use rarely did.

The defect is a hardware realization of the abstraction in claim-linnainmaa-rounding-error-problem: a single local arithmetic error propagating into an accumulated result. It sat beneath the arithmetic layer standardized by claim-kahan-8087-spec-became-ieee-754 — the divide instruction was IEEE-754-conformant in specification but not in silicon. The commercial fallout is treated in claim-intel-475m-charge-pentium-fdiv-recall.

Correction history.

• 2026-08-26 — This note previously stated the missing entries traced to "a lithography error" in a "programmable logic array," citing Pratt 1995. A direct re-read of Pratt's text (via 10-inbox/raw/2026-08-26-verify-the-pentium-fdiv-mechanism-and-the-nicely.md) found neither "lithography" nor "programmable logic array" anywhere in the source. Pratt instead reports Intel's own White Paper attribution ("a script that incorrectly copied values") without endorsing it, and raises his own alternative hypothesis. Title and body corrected to match the primary; the true cause is now flagged [unverified-mechanism — needs primary], routed to question-verify-intel-sb94-white-paper-fdiv-script-error. Also removed a sentence that had linked the (incorrect) "fabrication defect" framing to claim-euv-mirror-advantage-is-tacit-know-how-not-patent — both candidate causes now on record (a copying script, a misapplied threshold rule) are design/table-generation-time errors, not fabrication-process ones, so that analogy no longer holds.
• 2026-08-27 — This note's cause paragraph had, until now, rested on Pratt's secondhand report of Intel's attribution, flagged [unverified-mechanism — needs primary], with no exact Intel wording on record. A direct 32-page read of Sharangpani & Barton's own White Paper (10-inbox/raw/2026-08-27-verify-intels-own-white-paper-sharangpani-barton-1994.md, source_sha_2 above) confirms the script-error cause verbatim and corrects the acronym: Intel's own text spells "PLA" as "Programmable Lookup Array," not "Programmable Logic Array" as this note's earlier "lithography" framing had implied. The flag is discharged; status moved seedling → budding. See claim-intel-1994-white-paper-estimated-fdiv-bug-once-per-27000-years and claim-pratts-threshold-lowering-hypothesis-absent-from-intels-fdiv-white-paper for the rest of what that read found.