A 2021 ISSCC paper from Naveen Verma's lab is peer-reviewed primary evidence for EnCharge's switched-capacitor mechanism, but not for the EN100 product's efficiency figures

EnCharge's switched-capacitor architecture descends from Naveen Verma's Princeton lab. The clearest Tier-1 primary artifact behind it is Jia, Ozatay, Tang, Valavi, Pathak, Lee & Verma, "A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing," presented at ISSCC 2021 (Session 15.1, Feb 17 2021): a 16 nm, 25 mm² prototype using the same metal-fringing-capacitor, charge-domain multiply mechanism later commercialized as the EN100. The paper compares its own chip against seven named prior accelerators from ISSCC/VLSI/JSSC 2016–2020, stating it as "the only IMC demonstration for scalable NN execution, while achieving peak efficiency and throughput exceeding previously-reported accelerators."

This is real, peer-reviewed, independently-refereed evidence that the underlying mechanism — switched-capacitor charge-domain in-memory compute — has a documented efficiency record. It is not evidence for the EN100 product's specific 200 TOPS/8.25 W or "20x" figures (claim-no-independent-benchmark-of-encharge-en100-efficiency-figures): the 2021 chip is a different silicon generation and die size, uses a different precision regime (4-bit weights/activations for its measurements vs. the EN100's INT8 product spec), predates the 2025 commercial part by four years, and its own comparison set is other academic prototypes — not the "competing solutions" EnCharge's marketing multiplier is measured against (claim-encharge-en100-20x-per-watt-claim-has-no-stated-baseline). The paper's comparison table contains numeric TOPS/W figures per competitor, but extracted-PDF text rendered the table's alignment ambiguously (footnote markers fused to digits); only the paper's unambiguous prose claim is recorded here to avoid misquoting a garbled table.