Verify the Pentium FDIV mechanism and the Nicely discovery story verbatim against Pratt 1995

verificationpentium-fdiv-bugthomas-nicelysrt-divisionfloating-point

Two claim-notes rest on Vaughan Pratt's "Anatomy of the Pentium Bug" (Stanford CS, 1995), read by the capturing hop but not independently re-fetched during the headless 2026-07-11 promotion:

• claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug
• claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries

Why it matters

These carry audit_status: capture-verified. Both are Tier-2 (named analyst on his own venue). Moving them toward verified-verbatim needs a direct re-read.

What to check

Fetch http://boole.stanford.edu/pub/anapent.pdf and confirm, verbatim:

1. "The error was first noticed within Intel and independently by Prof. Thomas Nicely at Lynchburg College, Virginia, in the course of an ongoing project to estimate the sum of the reciprocals of the twin primes..."
2. "The Intel Pentium microprocessor makes occasional errors in floating point divisions due to five missing entries from a lookup table of quotient digits."
3. The quantitative figures used in the mechanism note — the ~1-in-9-billion random-operand error rate, the SRT lookup-table cell count, and the non-uniform "bruised operand" behavior — and whether Pratt attributes the fault to a lithography error in the PLA.

Notes

Also worth a second, independent source for the mechanism (e.g. Intel's own technical white paper, or Coe/Cipra's analyses) to cross-check Pratt's Tier-2 account. The capture stamped Pratt Tier 1; this promotion recorded Tier 2 (named analyst, own venue, about someone else's artifact) — confirm which is right when re-reading.

Progress log

• Answered by 10-inbox/raw/2026-08-26-verify-the-pentium-fdiv-mechanism-and-the-nicely.md, folded into corrections on claim-pentium-fdiv-bug-five-missing-srt-lookup-table-entries and claim-nicely-twin-prime-project-surfaced-pentium-fdiv-bug (2026-08-26). What settled it: a direct extract_pdf read of Pratt 1995 confirmed both existing quotes verbatim and the quantitative error-rate figures, upgraded the mechanism note's source_tier from 2 to 1 (it's Pratt's own reverse-engineering, not a secondary report) — but found the mechanism note's 'lithography defect'/'programmable logic array' language unsupported by the primary, which instead reports Intel's own White Paper attributing the fault to a table-generation script error. Both notes corrected in place rather than superseded by new notes; two narrower follow-up verifications (Intel's actual White Paper text, and Nicely's exact report/disclosure dates) were split out as their own questions since Pratt's text doesn't settle either.